`include "../define.svh"

module overflow_add (
    //input clk,
    //input sys_rst_n,
    input [1:0]data_type,
    input [23:0]m_norm_i,
    input signed [8:0]e_norm_i,
    output reg [7:0]e_out_final,
    output [22:0]m_out_final
);
        wire overflow;
        //reg [7:0]e_out_final;
    assign overflow = (data_type==`FP16) ? (e_norm_i>9'b000011110):(e_norm_i>9'b011111110);

    assign m_out_final = overflow ? (23'd0): (m_norm_i[22:0]);
    always @(*) begin
       if (overflow) begin
        case (data_type)
            `FP16: e_out_final=`FP16_INF_EXP;
            `FP32: e_out_final=`FP32_INF_EXP;
            default: e_out_final=8'd0;
        endcase
       end 
       else e_out_final=e_norm_i[7:0];
    end
/* 
    always @(posedge clk or negedge sys_rst_n) begin
        if (!sys_rst_n) begin
            e_out_final_reg<=8'd0;
            m_out_final_reg<=23'd0;
        end
        else begin
            e_out_final_reg<=e_out_final;
            m_out_final_reg<=m_out_final;
        end
    end */
endmodule